;***********************************************************************
;
; The objective of this Mini-Project is to .... < ? >
;
;
;
;
;***********************************************************************
;
;  Date code started: March 31, 2008
;
; Updatehistory (add an entry every time a significant change is made):
;
;  Date: < ? >  Name: < ? >   Update: < ? >
;
;  Date: < ? >  Name: < ? >   Update: < ? >
;
;  Date: < ? >  Name: < ? >   Update: < ? >
;
; ======================================================================
;
;  Variable declarations (SRAM)
;
;
        org        $3800
cur_row     	rmb     1
count   	rmb     1
count1          rmb     1
count2  	rmb     1
update  	rmb     1
tin     	rmb     1
tout    	rmb     1        ; SCI transmit display buffer OUT pointer
tsize   	equ     30        ; size of transmit buffer
tbuf    	rmb     tsize        ; SCI transmit display buffer
leftpb          rmb     1
rghtpb          rmb     1
prevpb          rmb     1

num_rows        equ	$08
ledlat          equ     $80      ; pin for display output latch


;***********************************************************************
;
; ASCII character definitions
;

RET         equ        $0d        ; return
LF          equ        $0a        ; line feed
NULL        equ        $00        ; null char


;========================================================================
;
; 9S12C32 REGISTER MAP

INITRM        EQU        $0010        ; INITRM - INTERNAL RAM POSITION REGISTER
INITRG        EQU        $0011        ; INITRG - INTERNAL REGISTER POSITION REGISTER

; ==== CRG - Clock and Reset Generator

SYNR        EQU        $0034        ; CRG synthesizer register
REFDV        EQU        $0035        ; CRG reference divider register
CRGFLG        EQU        $0037        ; CRG flags register
CRGINT        EQU        $0038
CLKSEL        EQU        $0039        ; CRG clock select register
PLLCTL        EQU        $003A        ; CRG PLL control register
RTICTL        EQU        $003B
COPCTL        EQU        $003C

; ==== SCI Register Definitions

SCIBDH        EQU        $00C8        ; SCI0BDH - SCI BAUD RATE CONTROL REGISTER
SCIBDL        EQU        $00C9        ; SCI0BDL - SCI BAUD RATE CONTROL REGISTER
SCICR1        EQU        $00CA        ; SCI0CR1 - SCI CONTROL REGISTER
SCICR2        EQU        $00CB        ; SCI0CR2 - SCI CONTROL REGISTER
SCISR1        EQU        $00CC        ; SCI0SR1 - SCI STATUS REGISTER
SCISR2        EQU        $00CD        ; SCI0SR2 - SCI STATUS REGISTER
SCIDRH        EQU        $00CE        ; SCI0DRH - SCI DATA REGISTER
SCIDRL        EQU        $00CF        ; SCI0DRL - SCI DATA REGISTER
PORTB        EQU        $0001        ; PORTB - DATA REGISTER
DDRB        EQU        $0003        ; PORTB - DATA DIRECTION REGISTER

timask          equ     $80             ; transmit interrupt mask
txdre           equ     $80             ; TDRE mask

; ==== ATD (analog to Digital) Converter / Pushbutton Digital Inputs

ATDCTL2        EQU        $0082        ; ATDCTL2 control register
ATDCTL3        EQU        $0083        ; ATDCTL3 control register
ATDCTL4        EQU        $0084        ; ATDCTL4 control register
ATDCTL5        EQU        $0085        ; ATDCTL5 control register
ATDSTAT        EQU        $0086        ; ATDSTAT0 status register

ATDDIEN        EQU        $008D        ; Port AD digital input enable
                        ; (programs Port AD bit positions as digital inputs)
PTADI        EQU        $008F        ; Port AD data input register 
                        ; (for reading digital input bits)
                        
PTAD    EQU     $0270   ; Port AD data register

PAD7            EQU     $80
PAD6            EQU     $40

ATDDR0        EQU        $0090        ; result register array (16-bit values)
ATDDR1         EQU        $0092
ATDDR2         EQU        $0094
ATDDR3         EQU        $0096
ATDDR4         EQU        $0098
ATDDR5         EQU        $009A
ATDDR6         EQU        $009C
ATDDR7         EQU        $009E

; ==== Direct Port Pin Access/Control - Port T

PTT        EQU        $0240        ; Port T data register
DDRT        EQU        $0242        ; Port T data direction register

; ==== TIM - Timer 16 Bit 8 Channels

TIOS        EQU        $0040        ;TIOS - TIMER INPUT CAPTURE/OUTPUT COMPARE SELECT
CFORC        EQU        $0041        ;CFORC - TIMER COMPARE FORCE REGISTER
OC7M        EQU        $0042        ;OC7M - OUTPUT COMPARE 7 MASK REGISTER
OC7D        EQU        $0043        ;OC7D - OUTPUT COMPARE 7 DATA REGISTER

TCNT        EQU        $0044
TCNTH        EQU        $0044
TCNTL        EQU        $0045

TSCR1        EQU        $0046        ;TSCR - TIMER SYSTEM CONTROL REGISTER
TTOV        EQU        $0047
TCTL1        EQU        $0048        ;TCTL1 - TIMER CONTROL REGISTER 1
TCTL2        EQU        $0049        ;TCTL2 - TIMER CONTROL REGISTER 3
TCTL3        EQU        $004A        ;TCTL3 - TIMER CONTROL REGISTER 3
TCTL4        EQU        $004B        ;TCTL4 - TIMER CONTROL REGISTER 3
TIE        EQU        $004C
TSCR2        EQU        $004D
TFLG1        EQU        $004E        ;TFLG1 - TIMER INTERRUPT FLAG 1
TFLG2        EQU        $004F        ;TFLG2 - TIMER INTERRUPT FLAG2

TC0        EQU        $0050        ;TC0 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER
TC1        EQU        $0052        ;TC1 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER
TC2        EQU        $0054        ;TC2 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER
TC3        EQU        $0056        ;TC3 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER
TC4        EQU        $0058        ;TC4 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER
TC5        EQU        $005A        ;TC5 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER
TC6        EQU        $005C        ;TC6 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER
TC7        EQU        $005E        ;TC7 - TIMER INPUT/CAPTURE COMPARE HIGH REGISTER

; ==== IMPORTANT -- Routing register for Port T (selects TIM vs PWM mapping)

MODRR        EQU        $0247        ; Port T module routing register        
                        ; NOTE: Used to select TIM or PWM mapping to Port T pins

; ==== PA - Pulse Accumulator

PACTL        EQU        $0060        ;PATCL - PULSE ACCUMULATOR CONTROL REGISTER
PAFLG        EQU        $0061        ;PAFLG - PULSE ACCUMULATOR FLAG REGISTER
PACNT        EQU        $0062        ;PACNT - PULSE ACCUMULATOR COUNT REGISTER

; ==== PWM - Pulse width Modulator

PWME         EQU        $00E0        ; PWM enable
PWMPOL         EQU        $00E1        ; PWM polarity
PWMCLK         EQU        $00E2        ; PWM clock source select
PWMPRCLK EQU        $00E3        ; PWM pre-scale clock select
PWMCAE         EQU        $00E4        ; PWM center align enable
PWMCTL         EQU        $00E5        ; PWM control (concatenate enable)
 
PWMSCLA         EQU        $00E8        ; PWM clock A scaler
PWMSCLB         EQU        $00E9        ; PWM clock B scaler

PWMPER0        EQU        $00F2        ; PWM period registers
PWMPER1        EQU        $00F3
PWMPER2        EQU        $00F4
PWMPER3        EQU        $00F5
PWMPER4        EQU        $00F6
PWMPER5        EQU        $00F7

PWMDTY0        EQU        $00F8        ; PWM duty registers
PWMDTY1        EQU        $00F9
PWMDTY2        EQU        $00FA
PWMDTY3        EQU        $00FB
PWMDTY4        EQU        $00FC
PWMDTY5        EQU        $00FD

; ==== SPI - Serial Peripheral Interface

SPICR1        EQU        $00D8        ;SPI0CR1 - SPI CONTROL REGISTER
SPICR2        EQU        $00D9        ;SPI0CR2 - SPI CONTROL REGISTER
SPIBR        EQU        $00DA        ;SPI0BR - SPI BAUD RATE REGISTER
SPISR        EQU        $00DB        ;SPI0SR - SPI STATUS REGISTER
SPIDR        EQU        $00DD        ;SPI0DR - SPI DATA REGISTER

; ==== Port M

PTM        EQU        $0250        ; Port M data register
PTIM        EQU        $0251        ; Port M input pin register
DDRM        EQU        $0252        ; Port M data direction register

; ======================================================================

REGBASE        EQU        $0        ; registers start at 0000
RAMBASE        EQU        $3800        ; 2KB SRAM located at 3800-3FFF

;***********************************************************************
;  BOOT-UP ENTRY POINT
;***********************************************************************

        org        $8000
startup        sei                        ; Disable interrupts
        movb        #$00,INITRG        ; set registers to $0000
        movb        #$39,INITRM        ; map RAM ($3800 - $3FFF)
        lds        #$3FCE                ; initialize stack pointer

;
; Set the PLL speed (bus clock = 24 MHz)
;

        bclr        CLKSEL,$80        ; disengage PLL from system
        bset        PLLCTL,$40        ; turn on PLL
        movb        #$2,SYNR        ; set PLL multiplier
        movb        #$0,REFDV        ; set PLL divider
        nop
        nop
plp        brclr        CRGFLG,$08,plp        ; while (!(crg.crgflg.bit.lock==1))
        bset        CLKSEL,$80        ; engage PLL 

;
; Disable watchdog timer (COPCTL register)
;
        movb        #$40,COPCTL        ; COP off; RTI and COP stopped in BDM-mode

;
; Initialize asynchronous serial port (SCI) for 9600 baud, no interrupts
;
        movb        #$00,SCIBDH        ; set baud rate to 9600
        movb        #$9C,SCIBDL        ; 24,000,000 / 16 / 156 = 9600 (approx)
        movb        #$00,SCICR1        ; $9C = 156
        movb        #$0C,SCICR2        ; initialize SCI with interrupts initially off

        movb        #$10,DDRB        ; set PB4 for output mode
        movb        #$10,PORTB        ; assert DTR pin on COM port


;***********************************************************************
;  START OF CODE FOR SPRING 2008 MINI-PROJECT
;***********************************************************************
;
;  Flag and variable initializations
        clr     count
        clr     count1
        clr     count2
        movb    $ff,update
        movb    #$ff,cur_row
        
        clr     tin
        clr     tout
        
        clr     leftpb
        clr     rghtpb
        
        movb    #$c0,prevpb



        
; Initialize digital I/O port pins
        movb    #$8f,DDRT                ; set up for output
        movb    #$30,DDRM                ; SPI output, possible PM0-PM3 I/O
        movb	#$c0,ATDDIEN                   ; set up for input
        
; Initialize RTI for 2.048 ms interrupt rate
        movb    #$1F,RTICTL             ; set RTI for 2.048 ms
        bset    CRGINT,$80              ; enable RTI and system IRQ interrupts

; Initialize TIM Ch 7 (TC7) for periodic interrupts every 1.000 ms
;    Enable timer subsystem
;    Set channel 7 for output compare
;    Set appropriate pre-scale factor and enable counter reset after OC7
;    Set up channel 7 to generate 1 ms interrupt rate
;    Initially disable TIM Ch 7 interrupts

        movb    #$80,TSCR1      ; enable timer
        movb    #$80,TIOS       ; set channel 7 output compare
        movb    #$0c,TSCR2      ; pre-scale=16, enable counter reset
        movw    #!1500,TC7       ; set interrupts for 10ms
        movb    #$80,TIE        ;enable T7 interrupt
        ;clr     TIE             ; disable T7 interrupt
        

; Initialize SPI
        movb    #$00,SPIBR      ; select 12 Mbps rate (24 MHz bus)
        ; Master mode, Interrupts off, CPOL=0,
        ; CPHA=0, slave select disabled, data
        ; transferred most significant bit first
        movb    #$50,SPICR1
        ; Normal (non-bidirectional) mode
        clr     SPICR2

; enable interrupts
        cli


main    brclr   leftpb,$01,chk_rght
        clr     leftpb
        
        ;decrement count2 by 1, wrap 0 to 25
        dec     count2
        ;ldaa    count2
        ;cmpa    #$ff
        ;bne     chk_rght
        ;movb    #!3,count2

chk_rght
        brclr   rghtpb,$01,cont
        clr     rghtpb

        ;increment count2 by 1, wrap 25 to 0
        inc     count2
        ;ldaa    count2
        ;cmpa    #!4
        ;bne     cont
        ;clr     count2

cont	ldaa        count
        tsta
        bne     main
        
        ldaa    #$08
        jsr     outchar
        ldaa    count2
        jsr     htoa
        jsr     outchar
        jmp     main

;***********************************************************************
;
;  TIM interrupt service routine
;
;  Initialized for 10.00 ms interrupt rate
;
;

tim_isr
        bset    TFLG1,$80       ; clear interrupt
        
        inc     cur_row
        ldaa    cur_row
        cmpa    #num_rows
        bne     refresh
        
        clr     cur_row
        clra
        
refresh
        ; save a for later
        psha

	; update row
        bclr    PTT,$0f         ; clear
        oraa    PTT             ; update
        staa    PTT             ; output

        ; load current row
        ldaa    count2
	ldab    #num_rows
        mul
        addd	#maze_map
        tfr     d,x
	pula
        ldaa	a,x
        
        
        ; if leds are active low
        ;coma

        ;send it to shift register
        jsr        spio
        
        ;latch value
lat     brclr   SPISR,$20,lat   ; wait until tx done
	bset    PTT,ledlat      ; open latch
        nop                     ; allow for latch setup time
        bclr    PTT,ledlat      ; close latch and lock value

        rti

;***********************************************************************
;
;  RTI interrupt service routine
;
;  Initialized for 2.048 ms interrupt rate
;
;

rti_isr
        bset    CRGFLG,$80      ; clear RTI device flag
        

sample_left
        ; check from high-to-low transition on left button
        brset   PTAD,PAD7,sample_right   ; branch if button not pressed
        brclr   prevpb,PAD7,sample_right ; no change, skip ahead
        bset    leftpb,$01             ; button pressed after de-bounce

sample_right
        ; check from high-to-low transition on right button
        brset   PTAD,PAD6,track_rnd     ; branch if button not pressed
        brclr   prevpb,PAD6,track_rnd        ; no change, skip ahead
        bset    rghtpb,$01              ; button pressed after de-bounce

track_rnd
        ; increment random value mod 12-bit
        inc     count
        ldaa    count
        bne     rti_exit
        
        inc     count1
        ldaa    count1
        cmpa    #!2
        bne     rti_exit
        clr     count1
        
        ;inc     count2
        ;ldaa    count2
        ;cmpa    #!26
        ;bne     rti_go_on
        ;clr     count2
        ;clra
        
rti_go_on


        

rti_exit
        movb    PTAD,prevpb
        rti
        
;***********************************************************************
; pmsg
;***********************************************************************
pmsg    puly
        ; load char
ploop   ldaa    1,y+
        ; check for null char
        beq     pexit
        ; put char in buffer
        jsr     outchar
        ; repeat
        bra ploop

pexit   pshy
        rts
        
;***********************************************************************
; Subroutine:        htoa
; Description:  converts the hex nibble in the A register to ASCII
; Input:        hex nibble in the A accumualtor
; Output:        ASCII character equivalent of hex nibble
; Reg. Mod.:        A, CC
;***********************************************************************

htoa    adda         #$90
        daa
        adca         #$40
        daa
        rts
        
;***********************************************************************
; Name:         outchar
; Description:  outputs ASCII character passed in the A register
;                  to the SCI serial port
;***********************************************************************

outchar brclr SCISR1,txdre,outchar
        staa   SCIDRL ; output ASCII character to SCI
        rts
        
;***********************************************************************
; spio
;       transmit data passed in A register
;***********************************************************************
spio    brclr   SPISR,$20,spio
        staa    SPIDR           ; transmit data
        rts


; character table map
maze_map        db      $01,$00,$00,$00,$00,$00,$00,$00
                db      $02,$00,$00,$00,$00,$00,$00,$00
                db      $04,$00,$00,$00,$00,$00,$00,$00
                db      $08,$00,$00,$00,$00,$00,$00,$00
                db      $10,$00,$00,$00,$00,$00,$00,$00
                db      $20,$00,$00,$00,$00,$00,$00,$00
                db      $40,$00,$00,$00,$00,$00,$00,$00
                db      $80,$00,$00,$00,$00,$00,$00,$00
                
		db      $00,$01,$00,$00,$00,$00,$00,$00
		db      $00,$02,$00,$00,$00,$00,$00,$00
		db      $00,$04,$00,$00,$00,$00,$00,$00
		db      $00,$08,$00,$00,$00,$00,$00,$00
		db      $00,$10,$00,$00,$00,$00,$00,$00
		db      $00,$20,$00,$00,$00,$00,$00,$00
		db      $00,$40,$00,$00,$00,$00,$00,$00
		db      $00,$80,$00,$00,$00,$00,$00,$00
		
		db      $01,$02,$04,$08,$10,$20,$40,$80
                db      $80,$40,$20,$10,$08,$04,$02,$01
		db      $01,$03,$07,$0f,$1f,$3f,$7f,$ff
                db      $ff,$fe,$fc,$f8,$f0,$e0,$c0,$80  ; triangle
                db      $07,$08,$08,$08,$07     ;C
                db 	$0e,$09,$09,$09,$0e     ;D
                db	$0f,$08,$0e,$08,$0f     ;E
                db	$0f,$08,$0e,$08,$08     ;F
                db	$07,$08,$0b,$09,$07     ;G
                db	$09,$09,$0f,$09,$09     ;H
                db	$0e,$04,$04,$04,$0e     ;I
                db	$03,$01,$01,$09,$06     ;J
                db	$09,$0a,$0c,$0a,$09     ;K
                db	$08,$08,$08,$08,$0f     ;L
                db	$09,$0f,$0d,$09,$09     ;M
                db	$09,$0d,$0b,$09,$09     ;N
                db	$06,$09,$09,$09,$06     ;O
                db	$0e,$09,$0e,$08,$08     ;P
                db	$06,$09,$09,$0a,$05     ;Q
                db	$0e,$09,$0e,$09,$09     ;R
                db	$07,$08,$06,$01,$0e     ;S
                db	$0f,$04,$04,$04,$04     ;T
                db	$09,$09,$09,$09,$06     ;U
                db	$09,$09,$0a,$0c,$08     ;V
                db	$09,$09,$09,$0d,$0a     ;W
                db	$09,$06,$06,$09,$09     ;X
                db	$09,$09,$06,$04,$04     ;Y
                db	$0f,$02,$04,$08,$0f     ;Z
                
                
                
;***********************************************************************
;
; Define 'where you want to go today' (reset and interrupt vectors)
;
; If get a "bad" (undefined) interrupt, just return from it

BadInt        rti

; ------------------ VECTOR TABLE --------------------

        org        $FF8A
        fdb        BadInt        ;$FF8A: VREG LVI
        fdb        BadInt        ;$FF8C: PWM emergency shutdown
        fdb        BadInt        ;$FF8E: PortP
        fdb        BadInt        ;$FF90: Reserved
        fdb        BadInt        ;$FF92: Reserved
        fdb        BadInt        ;$FF94: Reserved
        fdb        BadInt        ;$FF96: Reserved
        fdb        BadInt        ;$FF98: Reserved
        fdb        BadInt        ;$FF9A: Reserved
        fdb        BadInt        ;$FF9C: Reserved
        fdb        BadInt        ;$FF9E: Reserved
        fdb        BadInt        ;$FFA0: Reserved
        fdb        BadInt        ;$FFA2: Reserved
        fdb        BadInt        ;$FFA4: Reserved
        fdb        BadInt        ;$FFA6: Reserved
        fdb        BadInt        ;$FFA8: Reserved
        fdb        BadInt        ;$FFAA: Reserved
        fdb        BadInt        ;$FFAC: Reserved
        fdb        BadInt        ;$FFAE: Reserved
        fdb        BadInt        ;$FFB0: CAN transmit
        fdb        BadInt        ;$FFB2: CAN receive
        fdb        BadInt        ;$FFB4: CAN errors
        fdb        BadInt        ;$FFB6: CAN wake-up
        fdb        BadInt        ;$FFB8: FLASH
        fdb        BadInt        ;$FFBA: Reserved
        fdb        BadInt        ;$FFBC: Reserved
        fdb        BadInt        ;$FFBE: Reserved
        fdb        BadInt        ;$FFC0: Reserved
        fdb        BadInt        ;$FFC2: Reserved
        fdb        BadInt        ;$FFC4: CRG self-clock-mode
        fdb        BadInt        ;$FFC6: CRG PLL Lock
        fdb        BadInt        ;$FFC8: Reserved
        fdb        BadInt        ;$FFCA: Reserved
        fdb        BadInt        ;$FFCC: Reserved
        fdb        BadInt        ;$FFCE: PORTJ
        fdb        BadInt        ;$FFD0: Reserved
        fdb        BadInt        ;$FFD2: ATD
        fdb        BadInt        ;$FFD4: Reserved
        fdb        BadInt        ;$FFD6: SCI Serial System
        fdb        BadInt        ;$FFD8: SPI Serial Transfer Complete
        fdb        BadInt        ;$FFDA: Pulse Accumulator Input Edge
        fdb        BadInt        ;$FFDC: Pulse Accumulator Overflow
        fdb        BadInt        ;$FFDE: Timer Overflow
        fdb        tim_isr       ;$FFE0: Standard Timer Channel 7
        fdb        BadInt        ;$FFE2: Standard Timer Channel 6
        fdb        BadInt        ;$FFE4: Standard Timer Channel 5
        fdb        BadInt        ;$FFE6: Standard Timer Channel 4
        fdb        BadInt        ;$FFE8: Standard Timer Channel 3
        fdb        BadInt        ;$FFEA: Standard Timer Channel 2
        fdb        BadInt        ;$FFEC: Standard Timer Channel 1
        fdb        BadInt        ;$FFEE: Standard Timer Channel 0
        fdb        rti_isr       ;$FFF0: Real Time Interrupt (RTI)
        fdb        BadInt        ;$FFF2: IRQ (External Pin or Parallel I/O) (IRQ)
        fdb        BadInt        ;$FFF4: XIRQ (Pseudo Non-Maskable Interrupt) (XIRQ)
        fdb        BadInt        ;$FFF6: Software Interrupt (SWI)
        fdb        BadInt        ;$FFF8: Illegal Opcode Trap ()
        fdb        startup        ;$FFFA: COP Failure (Reset) ()
        fdb        BadInt        ;$FFFC: Clock Monitor Fail (Reset) ()
        fdb        startup        ;$FFFE: /RESET
        end

;***********************************************************************
; ECE 362 - Mini-Project ASM Source File - Spring 2008
;***********************************************************************